High-Performance Computing For Silicon Design
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چکیده
Since deployment, our HPC environment has supported a 13x increase in compute demand, with a 10x increase in stability. In addition, tapeout time was reduced from 25 days for the first 65-nm process technologybased microprocessor in a non-HPC compute evironment to 10 days for the first 45-nm process technology-based microprocessor in an HPC-enabled envirnoment. The success of the HPC environment was due to factors such as careful alignment of technology with business needs, informed risk taking, and disciplined execution. We are continuing to develop the next HPC generation to enable tapeout of 22-nm Intel processors. Shesha Krishnapura Senior Principal Engineer, Intel IT
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